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Intel CPU Design Requires Rework

Pat Gelsinger, delivering the keynote at the 41st Design Automation Conference here, outlined the many challenges facing designers in the coming years, from gate and source-drain leakage problems to funky and vexing variability issues which cannot be managed by contemporary tools. “We believe our design methodologies and our design tools need to be fundamentally reconsidered,” Gelsinger said. The issues of power dissipation and process and on-chip variations are thorny ones that require new ways of thinking. While gate oxide thinness should be solved with high-k dielectrics, the problems of source-drain leakage are increasing exponentially. To deal with it, Intel is looking at tri-gate structures to mitigate leakage.

Pat Gelsinger, delivering the keynote at the 41st Design Automation Conference here, outlined the many challenges facing designers in the coming years, from gate and source-drain leakage problems to funky and vexing variability issues which cannot be managed by contemporary tools. “We believe our design methodologies and our design tools need to be fundamentally reconsidered,” Gelsinger said. The issues of power dissipation and process and on-chip variations are thorny ones that require new ways of thinking. While gate oxide thinness should be solved with high-k dielectrics, the problems of source-drain leakage are increasing exponentially. To deal with it, Intel is looking at tri-gate structures to mitigate leakage.

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